5720584
9780123739735
System-on-Chip Test Architectures: Nanometer Design for Testability
by Wang, Laung-Terng, Touba, Nur, Stroud, Charles
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Product details
- ISBN-13: 9780123739735
- ISBN: 012373973X
- Publication Date: 2007
- Publisher: Elsevier Science & Technology Books
AUTHOR
SUMMARY
This text is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.Wang, Laung-Terng is the author of 'System-on-Chip Test Architectures: Nanometer Design for Testability', published 2007 under ISBN 9780123739735 and ISBN 012373973X.
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