Verilog Digital System Design RT Level Synthesis, Testbench and Verification

This title isn't a simplistic introduction to the popular hardware description language, but rather a rigorous tutorial showing designers how to deploy Verilog in sophisticated digital system designs. This new second edition completely updates the book and the many worked examples for the new standard Verilog 2001, as well as including new synthesis standards and detailing the new OVL verification library. Used as both a designer's reference and an advanced text, the book will include a CD-ROM of simulation tools and code examples, and a complete instructor's manual for professors.Navabi, Zainalabedin is the author of 'Verilog Digital System Design RT Level Synthesis, Testbench and Verification', published 2005 under ISBN 9780071445658 and ISBN 007144565X.