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This book explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.Bening, Lionel is the author of 'Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in VERILOG - Lionel Bening - Hardcover' with ISBN 9780792377887 and ISBN 0792377885.
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